1. Field of the invention
The present invention relates generally to a method and an apparatus wherein hierarchical graphic data is employed for designing a semiconductor integrated circuit. More particularly, the invention relates to a method for managing logical information in a front-end tool, which is employed in a computer aided design apparatus (CAD) for designing a large scale integrated (LSI) circuit.
2. Description of the Related Art
Generally, when designing an LSI circuit by means of a CAD system, a computer program is formed from a net list of circuit parameters which describes the design of the circuit. The net list most generally utilizes a plurality of subprograms or macros corresponding to models of functional circuit elements or individual circuit cells (hereinafter referred to as a cell). Usually, the first design operation is to specify in the net list one or more macros or cells used in the circuit's construction. Next, each of the macros is divided into minute macros and the operation for designing each of the minute macros is carried out.
The overall of use of such a net list, as conventionally used in semiconductor design, is illustrated as shown in the block diagram of FIG. 6. Generally such net lists are created and defined according to the particular design parameters assigned to the various subcircuits and circuit elements (macros and cells, respectively) included in a particular semiconductor. Consequently, a net list is defined in part by the names of the macros or cells that are employed. Each of the macros is in turn defined by the particular input/output pins employed by the semiconductor and by the names of the nets that couple to the pins.
Table 1 shows an example of a hierarchical net list. In this particular net list, the controlling macro is defined by the name "CHIP". The "CHIP" is further defined by minute or user defined macros A, B as well as cell C. Each of the user defined macros and cell represent individual circuits or circuit elements respectively, and are defined in the net list to achieve a particular circuit function.
TABLE 1 ______________________________________ NAME : CHIP ; INPUTS : . 14 ; OUTPUTS : . 15 , . 16 , . 17 ; TYPES ; MACRO A : A ; MACRO B : B ; CELL C : C ; ENDTYPES ; NETS ; 001 : . 14 , A. 9 ; 002 : A. 10 , B. 11 ; C. 7 ; 003 : C. 8 , . 15 ; 004 : B. 12 , . 16 ; 005 : B. 13, . 17 ; ENDNETS ; ENDNAME ; (MACRO A) NAME : A ; INPUTS : . 9 ; OUTPUTS : . 10 ; TYPES ; CELL D : D ; ENDTYPES ; NETS ; 001 : . 9 , D. 1 ; 002 : . 10 , D. 2 ; ENDNETS ; ENDNAME ; (MACRO B) NAME : B ; INPUTS : . 11 ; OUTPUTS : . 12 ; TYPES ; CELL E : E ; CELL F : F ; ENDTYPES ; NETS ; 001 : . 11 , E. 3 , F. 5 ; 002 : E. 4 , . 12 ; 003 : F. 6 , . 13 ; ENDNETS ; ENDNAME ; ______________________________________
A specific logic file for every macro is then created for use in the hierarchical net list. These logic files 12, are used to generate a corresponding logic development file 13 representing the final desired semiconductor chip design or layout. Should the design results happen to be unsatisfactory to the designer, the logic development file can be decompiled and revised in redeveloped net list 20.
FIG. 7 is illustrative of the layout of circuit elements and fundamental logic cells on a semiconductor chip 14, designed using a hierarchical net list like that illustrated in table 1. A logic development file 15 corresponding to the layout of semiconductor chip 14 file is illustrated by FIG. 8, and comprises a top macro table 16, cell table 17, cell pin table 18, and net table 19.
The controlling macro table 16 stores the information relating to the chip specified as "CHIP" and includes such parameters as the number of the input/output pins and the output level with respect to that of the input level, etc. The cell table 17 stores the information relating to the cells C, D, E, F as chosen by the designer. The cell D is a cell that is employed in the user's macro A. The cells E, F are cells that are employed in the user's macro B. The cell C is coupled with the chip "CHIP" via a multi-table pointer 16a. The cells C through F are serially coupled via pointers 17a through 17c and are defined without regards to any previous or more general macros or data. The cell pin table 18 stores the information relating to the input/output pins D1, D2, E3, E4, F5, F6, C7, C8, CH14, CH15, CH16, CH17 also as chosen by the designer. The CH14, CH15, CH16, CH17 are input/output pins disposed in the semiconductor chip 14. In the net list, CH thereof is indicated by an independent ".". The net table 19 stores the information relating to the nets N1 through N5 that couple with the corresponding input/output pins, respectively.
Such conventionally developed net lists, as described above, are not designed having a hierarchical structure. Rather, they utilize a single dimensional structure having cells C, D, E, F that include data describing only a single element or circuit function. None include any predevelopment based upon any intermediate stage, such as user defined macro A or B.
Table 2 illustrates the appearance of a net list 20 decompiled from a logic development file 15. Such a decompiled net list would be desired when, for example, an unsatisfactory design result was obtained from the logic development file 13. From this decompiled net list 20, the design of the semiconductor chip 14 and the overall structure of the logic development file could be altered.
TABLE 2 ______________________________________ NAME : CHIP ; INPUTS : . 14 ; OUTPUTS : . 15 , . 16 , . 17 ; TYPES ; CELL D : D ; CELL E : E ; CELL F : F ; ENDTYPES ; NETS ; 001 : . 14 , D. 1 ; 002 : D. 2 , C. 7 ; E. 3 , F. 5 ; 003 : C.8 , . 15 ; 004 : E. 4 , . 16 ; 005 : F. 6 , . 17 ; ENDNETS ; ENDNAME ; ______________________________________
Thus in one sense, the conventional logic development file is itself an independent macro having no connection or relation to any of a myriad of user defined macros which may be available for use in any given semiconductor design.
Generally, conventional logic development files include only the cell level units defined at the most basic model level. This is to be contrasted with the hierarchical net list as shown in FIG. 9 where, for example, the I/O (i.e., input/output) macros 22, 23, and 24 are formed using the cells G and H; cells G and I; and cells G and J respectively.
However, if a net list is developed using conventional techniques, only the cells G, H, I, J would be utilized in creating a logic development file, without the benefits of macros 22 through 24. The immediate disadvantage of this occasions is the absence, in the logic development file itself, of any tangentially relevant circuit information, such as for example, industry standards for evaluating the operability of various components used in constructing semiconductors. Conventionally, such standards must be stored in files distinct from the logic development file. Therefore, for example, standard semiconductor components comprising many individual circuit cells can be evaluated by appropriate and corresponding evaluative parameters existing in a user defined macro unit. However, these parameters usually only stored in a different file from the logic development file.
FIG. 10 shows an examined standard file 25 that indicates parameters utilized during a circuit evaluation with respect to the I/O (input/output) of a user defined macro. For example, standard parameter data respecting a pin X in the semiconductor chip 21 as shown in FIG. 9 is to be taken out from the file 25. The blocks labeled 101, 102, 103 are test execution circuits, respectively. In this case, the cell H coupled with the cell G is searched from the developed net list through the net. A rather difficult method is executed for taking out a standard value "201" from the file 25, based on the combination of the cells G, H.
Further, in the conventional developing logic file, a macro X defined by the cells K, L as shown in FIG. 11 is unavailable for use in circuit evaluation. Only delay values relating to the cells K, L, as indicated by the parenthesized numbers, and the net lists exist. Consequently, the circuit simulation should be carried out by determining the delay values of the cells K, L and the net, respectively.
Conventionally, additional circuit parameters must be added to the logic development file in order to achieve a simple execution of the circuit's simulation. This makes it difficult for the designer when he desires to change or alter the schematic description of the net list. An additional difficulty is that such alterations to the design must be preformed without changing the overall desired characteristics of the LSI circuit.
Conventionally, to confirm whether an altered or changed net list produces equivalent overall LSI circuit results, the logic development file is often decompiled into the net list 20, as shown in FIG. 6. However, if the developing logic file 15 as shown in FIG. 8 is returned into the net list, only the ichnographically developed net list is presented for review without the benefit of allowing intermediate stages such a macro creation to be examined.
In the past, it has often been difficult to compare a redeveloped net list as shown in FIG. 6 with the hierarchical net list shown in Table 1. With the increase integration of circuit components in todays semiconductors, it is increasingly difficult for circuit designers to confirm that overall semiconductor design characteristics remain unchanged upon adding or deleting circuit components from the net list.
Furthermore, a conventional logic development file has a unidimensional structure that is entirely formed with very basic logic cell units such as AND or OR gates. With such basic units, the net list description and the data which must be made available to evaluate the net list data becomes excessively large. Consequently, as the number of files increases, more hardware is required to handle the increase, the manufacturing cost increases, and, as the access time to the required files increases, operational speed of the CAD design program decreases. Moreover, as the operation for managing conventional design system becomes increasingly complicated, the designer is faced with the additional problem of file designation. Meticulous care must be maintained to properly designate the multiplicity of files needed to preform the circuit design.